Optimal voltages and sizing for low power [CMOS VLSI]

Author

Stan, Mircea R.

Author_Institution

Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA

fYear

1999

fDate

7-10 Jan 1999

Firstpage

428

Lastpage

433

Abstract

We provide analytical “back of the envelope” calculations for the choice of optimal supply and threshold voltages and sizing for minimum energy-delay product. Based on such calculations we then show that a circuit design style with separate logic and buffer stages offers a better energy-delay product in the presence of interconnect parasitics

Keywords

CMOS integrated circuits; VLSI; circuit optimisation; delays; integrated circuit design; integrated circuit interconnections; low-power electronics; CMOS; VLSI; buffer stages; circuit design style; energy-delay product; interconnect parasitics; logic stages; minimum energy-delay product; optimal supply; optimal threshold voltages; CMOS technology; Energy consumption; Frequency; Integrated circuit interconnections; Logic design; Parasitic capacitance; Power supplies; Subthreshold current; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Conference_Location

Goa

ISSN

1063-9667

Print_ISBN

0-7695-0013-7

Type

conf

DOI

10.1109/ICVD.1999.745193

Filename

745193

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2553271