Title :
An approach for analytical modeling and simulation of gate all around MOSFET for 50 nm technology
Author :
Ghosh, Dhruba ; Bhulania, Paurush ; Kumar, Sunil
Author_Institution :
Amity Univ., Noida, India
Abstract :
This paper presents the analytical modeling of Gate All Around MOSFET using the Poisson´s equation. Gate All Around MOSFET is experimentally demonstrated using a silicon channel. The analyzed model shows the close agreement with the simulation results. Atlas-3D tool has been used for the numerical simulations. A good performance has been achieved by scaling of the channel length to 50 nm with top-down approach. Our designed MOSFET follows the traditional MOSFET behavior inspite of enormous scaling and negligible hot carrier effects. The proposed model gives the simplest analysis in comparison to quantum models. Leakage current is negligible due to the use of bulk substrate which easily suppressed the adverse effect of parasitic capacitance. Simulated graph strongly follows the parabolic equation along the channel region for surface potential.
Keywords :
MOSFET; Poisson equation; elemental semiconductors; graph theory; hot carriers; leakage currents; numerical analysis; parabolic equations; semiconductor device models; silicon; Atlas-3D tool; Poisson´s equation; Si; bulk substrate; channel length; gate all around MOSFET; hot carrier effects; leakage current; numerical simulations; parabolic equation; quantum models; silicon channel; size 50 nm; Analytical models; Electric potential; Logic gates; MOSFET; Mathematical model; Semiconductor device modeling; Silicon; Atlas-3D; Drain Induced barrier lowering; Gate All Around MOSFET; Mobility Reduction Model; Poisson´s equation; Quantum Mechanical Effects; Schottky barrier; Subthreshold swing;
Conference_Titel :
Signal Processing and Integrated Networks (SPIN), 2015 2nd International Conference on
Conference_Location :
Noida
Print_ISBN :
978-1-4799-5990-7
DOI :
10.1109/SPIN.2015.7095381