Effective die-package-PCB co-design methodology and its deployment in 10 Gbps serial link transceiver FPGA packages

This paper discusses the die-package-PCB co-design methodology and proposes an effective modeling technique for package-PCB co-simulation. This technique accurately takes into account the discontinuities at the package-PCB interface. The proposed new methodology renders the co-simulation 2-5X less time consuming than traditional practice. Based on the new methodology, a multi-layer multi-channel BGA package is designed for 10 Gbps FPGA applications. The differential return loss and insertion loss of the optimized package considering PCB and die effect are simulated, so are the cross talk between high-speed transceiver channels and jitter degradation of the transceiver channels due to the interference of the neighboring lower speed fabric I/Os.