A mixed analog/digital asynchronous processor for cortical computations in 3D SOI-CMOS

Author

Georgiou, Julius ; Andreou, Andreas G. ; Pouliquen, Philippe O.

Author_Institution

Dept. of Electr. & Comput. Eng., Cyprus Univ., Nicosia

fYear

2006

fDate

21-24 May 2006

Abstract

We present a system level architecture for a scalable, mixed-signal, asynchronous processor, aimed at cortical computations. The design has been implemented in MIT Lincoln Lab´s three-tier SOI-CMOS 0.18mum digital process. The main circuits are distributed in the two tiers; an asynchronous address-event based read/write middle tier and an odd symmetric spatial filter (8 orientations) on the bottom tier. The top tier includes a photosensitive pixel array (64times64) to facilitate testing and characterization of the system. A highspeed 2-phase asynchronous chip-to-chip communication protocol is built-in to facilitate system scalability

Keywords

CMOS integrated circuits; asynchronous circuits; microprocessor chips; mixed analogue-digital integrated circuits; 0.18 micron; 3D SOI-CMOS; asynchronous processor; communication protocol; cortical computations; digital circuits; mixed analog-digital processor; system level architecture; system scalability; Analog computers; Circuits; Computer architecture; Frequency; Neuromorphics; Neurons; Protocols; Scalability; Spatial filters; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693743

Filename

1693743