DocumentCode :
2553881
Title :
Test generation for analog circuits using partial numerical simulation
Author :
Variyam, Pramodchandran N. ; Hou, Junwie ; Chatterjee, Abhijit
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
1999
fDate :
7-10 Jan 1999
Firstpage :
597
Lastpage :
602
Abstract :
In this paper, we present a novel test generation strategy based on partial numerical fault simulation. Existing fault-based test generation methodologies for analog circuits are based on accurate but expensive fault simulation. In the proposed methodology, fault simulation is terminated before convergence for reasons of simulation speed. The relative fitness of various input stimuli is evaluated based on the results of this partial numerical simulation. A comparison of this new methodology with existing accurate fault simulation based test generation methods, shows up to 15 times speed-up in test generation
Keywords :
analogue integrated circuits; automatic test pattern generation; fault simulation; integrated circuit testing; analog circuits; fault simulation; fault-based test generation; input stimuli; partial numerical simulation; simulation speed; test generation times; Analog circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; DC generators; Electrical fault detection; Fault detection; Numerical simulation; Performance evaluation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location :
Goa
ISSN :
1063-9667
Print_ISBN :
0-7695-0013-7
Type :
conf
DOI :
10.1109/ICVD.1999.745220
Filename :
745220
Link To Document :
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