• DocumentCode
    2553897
  • Title

    Silicon-level physical verification of SubWavelengthTM designs

  • Author

    Chang, Fang-Cheng ; Kwok, Melissa ; Rachlin, Kenneth ; Pack, Robert

  • Author_Institution
    Numerical Technol. Inc., Santa Clara, CA, USA
  • fYear
    1999
  • fDate
    7-10 Jan 1999
  • Firstpage
    603
  • Lastpage
    605
  • Abstract
    In this paper, we show that the use of SubWavelength mask design for improved IC performance and yield presents new challenges for traditional deep submicron ECAD physical verification tools. We demonstrate the need for new approaches and propose two tools for the silicon-level physical verification of SubWavelength designs. Fortunately, these tools work within current physical verification design flows
  • Keywords
    ULSI; circuit layout CAD; integrated circuit layout; integrated circuit yield; masks; photolithography; ECAD physical verification tools; IC yield; SubWavelength mask design; deep submicron technology; physical verification design flows; silicon-level physical verification; CMOS integrated circuits; Electronic design automation and methodology; Integrated circuit layout; Lithography; Manufacturing processes; Optical design; Optical distortion; Photonic integrated circuits; Silicon; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1999. Proceedings. Twelfth International Conference On
  • Conference_Location
    Goa
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-0013-7
  • Type

    conf

  • DOI
    10.1109/ICVD.1999.745221
  • Filename
    745221
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2553897