Title :
Novel design of ternary magnitude comparator using CNTFETs
Author :
Murotiya, S.L. ; Gupta, A. ; Vasishth, S.
Author_Institution :
Electr. & Electron. Dept., Birla Inst. of Technol. & Sci., Pilani, India
Abstract :
This paper proposes a novel design of 1-bit ternary magnitude comparator (TMC) using carbon nano tube field effect transistors (CNTFETs). The proposed 1-bit TMC is designed for pass transistor logic style in order to achieve low transistor count. Further, proposed design is used in realization of n-bit TMC which utilizes static binary tree configuration to correct the voltage levels and minimizes the number of stages to get high performance. Synopsis Hspice simulation results demonstrate that the proposed TMC for 4-bit operand length is 15% faster or 14% energy efficient with 32% less number of transistors, in comparison with CNTFET-based designs, recently published in the literature.
Keywords :
SPICE; carbon nanotube field effect transistors; comparators (circuits); ternary logic; C; CNTFET; Hspice simulation; carbon nano tube field effect transistors; design; low transistor count; pass transistor logic style; static binary tree configuration; ternary magnitude comparator; word length 1 bit; CNTFETs; Delays; Integrated circuit modeling; Load modeling; Logic gates; Multivalued logic; carbon nano tube (CNT) field effect transistor (CNTFET); ternary logic; ternary magnitude comparator (TMC);
Conference_Titel :
India Conference (INDICON), 2014 Annual IEEE
Conference_Location :
Pune
Print_ISBN :
978-1-4799-5362-2
DOI :
10.1109/INDICON.2014.7030447