CMOS analog iterative decoders using margin propagation circuits

Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power consumption. The current state of art CMOS analog decoders uses MOS transistors biased in weak inversion which limits their speed of operation. In this paper a novel analog decoding network is presented which can operate with MOS transistor biased both in weak and strong inversion. The principle of operation is based on margin propagation algorithm which requires only addition, subtraction and thresholding operation which can be easily implemented in analog VLSI. A current mode implementation of the decoder is proposed which operates directly in log-likelihood space. This not only improves the speed of convergence for iterative decoding but also enhances the dynamic range of the decoder. Simulation based on a simple tail-biting trellis is presented that demonstrate the decoding characteristic and speed of operation of the proposed margin propagation network