A straightforward method to determine the parasitic gate resistance of GaN FET

In this paper a straightforward method to determine the parasitic gate resistance (R_g) of GaN FET is introduced. The method uses a simple linear regression to directly determine the value of R_g without prior knowledge of the Schottky diode resistance R₀ and capacitance C₀. Furthermore, the method requires only a single bias point with low DC current at the gate. In addition to this straightforward method, a reliable procedure for extracting the parasitic source inductance L_S is also introduced. This procedure for extracting the source inductance is useful for GaN FET when the imaginary part of Z₁₂ is negative. The new method has been used successfully in the parasitic element characterization of power AlGaN/GaN HFETs.