Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

As semiconductor technology is scaled and voltage level is reduced, the impact of power supply variation has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable since there is a high correlation between delay and supply voltage. Supply noise analysis has often used a vector-based STA approach. However, vector-based approaches are very expensive, particularly during the design phase. In this work, two novel vectorless approaches are described such that circuit delay increases due to power supply noise can be efficiently estimated. Experimental results on ISCAS89 circuits show not only the accuracy of our approaches, but also the indispensability of considering care-bits, which sensitize the longest paths during the power supply noise analysis.