Title :
Radiation hardened 32-bit RISC microprocessor
Author :
Hwang, Andrew S.
Author_Institution :
Space & Electron. Group, TRW Inc., Redondo Beach, CA, USA
Abstract :
TRW has developed a single chip radiation hardened 32-bit RISC microprocessor, the RH32S. The RH32S is based on TRW´s 5-chip version. It has over five million transistors and is implemented using 0.35 μm SOI standard cell technology. The high-performance architecture provides greater than 40 million instructions per second (MIPS) at 50 MHz while only using six watts of power. The RH32S is ideal for space and airborne applications requiring data handling, real-time control, and on-board data analysis. It is currently being designed into multiple flight systems
Keywords :
CMOS digital integrated circuits; aircraft computers; boundary scan testing; built-in self test; cellular arrays; design for testability; fault tolerant computing; microprocessor chips; pipeline processing; programming environments; radiation hardening (electronics); reduced instruction set computing; silicon-on-insulator; space vehicle electronics; storage management chips; 32 bit; 40 MIPS; 6 W; BIST; RISC microprocessor; SOI CMOS; SOI standard cell technology; airborne application; boundary scan; data handling; fault tolerance; high-performance architecture; memory management units; multiple flight systems; on-board data analysis; processor execution pipelines; real-time control; single chip radiation hardened; software development environment; space application; testability; Aerospace electronics; Central Processing Unit; Fault tolerance; Memory management; Microprocessors; Monitoring; Radiation hardening; Reduced instruction set computing; Silicon on insulator technology; Space technology;
Conference_Titel :
Aerospace Conference Proceedings, 2000 IEEE
Conference_Location :
Big Sky, MT
Print_ISBN :
0-7803-5846-5
DOI :
10.1109/AERO.2000.878493
