The design and verification of a VLSI chip for electrocardiogram data compression

Author

Roy, S.C. ; Krakow, W.T. ; Sacks, B. ; Batchelor, W.E. ; Bohs, L.N. ; Barr, R.C.

Author_Institution

Microelectron. Center of North Carolina, Research Triangle Park, NC, USA

fYear

1990

fDate

3-6 Jun 1990

Firstpage

170

Lastpage

177

Abstract

A VLSI architecture for performing electrocardiogram (ECG) data compression is presented. The goals of the chip are to improve both the speed and the density as compared to an off-the-shelf implementation. The complex control sections of the chip were synthesized from a functional description into standard cells, while critical-path arithmetic sections were custom designed. This mix of full custom and standard cell design allows for a trade-off between design time and area, with no penalty in speed performance. The resulting silicon chip, implemented in 1.1 μm CMOS technology, is useful for ECG data collection, compression, and analysis

Keywords

VLSI; biomedical electronics; data compression; electrocardiography; CMOS technology; VLSI chip design; VLSI chip verification; critical-path arithmetic sections; electrocardiogram data compression; full custom design; speed performance; standard cell design; Biomedical engineering; Compression algorithms; Data compression; Electrocardiography; Frequency; Mathematics; Microelectronics; Sampling methods; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Based Medical Systems, 1990., Proceedings of Third Annual IEEE Symposium on

Conference_Location

Chapel Hill, NC

Print_ISBN

0-8186-9040-2

Type

conf

DOI

10.1109/CBMSYS.1990.109396

Filename

109396