A 0.18/spl mu/m CMOS clock and data recovery circuit with extended operation range

Author

Li, Miao ; Huang, Wenjie ; Kwasniewski, Tad ; Wang, Shoujun

Author_Institution

Dept. or Electron., Carleton Univ., Ottawa, Ont.

fYear

2006

fDate

21-24 May 2006

Lastpage

5142

Abstract

A clock and data recovery architecture for highspeed communication systems is proposed. Based on early-late method, the bang-bang phase and frequency detectors work in two modes: half-rate mode and quarter-rate mode, thus a large applicable data rate range is available. Simulated in a 0.18mum CMOS technology, the circuit exhibits a peak-to-peak jitter of 48ps in the recovered quarter-rate clock with PRBS length of 2¹⁵-1 at 6.25-Gb/s. The data is recovered and demultiplexed inherently. In quarter-rate mode, the power dissipation is 80mW from a 1.8V supply

Keywords

CMOS digital integrated circuits; clocks; phase detectors; synchronisation; 0.18 micron; 1.8 V; 6.25 Gbit/s; 80 mW; CMOS clock recovery circuit; bang-bang phase detectors; data recovery circuit; frequency detectors; highspeed communication systems; Automatic control; CMOS technology; Circuit simulation; Clocks; Frequency locked loops; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693789

Filename

1693789