EM-based modeling of Cascode FETs suitable for MMIC design

Cascode FETs are widely used in the design of MMICs, owing to their almost unilateral behavior. An accurate model of the cell is indeed necessary in order to achieve good circuit performance estimations. In the literature, the Cascode cell models are usually obtained on the basis of measurements of the entire structure or by a preliminary characterization of the common source elementary cell. However, the different influence of the parasitic network between common source and common gate topologies are not taken into account in the latter case. In this paper, a distributed approach based on EM simulations is adopted for the modeling of the parasitic network of the Cascode cell. The proposed procedure leads to a well conditioned characterization of the intrinsic devices, which can be used for the modeling of both the common source and the common gate transistors. Wide experimental validation is provided in the paper.