A clock recovery circuit for blind equalization multi-Gbps serial data links

This paper presents a clock recovery circuit for multi-Gbps serial data link that extracts the timing information hidden in pulse amplitude modulation by exploiting its intrinsic cyclostationarity. In contrast to conventional clock recovery circuit based on phase detector of Alexander or Hogge type, the proposed one is compatible with multi-level PAM data and linearly distorted data with closed eye diagram, and does not convert the inter-symbol interference into timing jitter. Hence it is well suited to be integrated as an a priori clock generator in a blind equalizer of a multi-Gbps serial link receiver. The operation principles with related theoretical background as well as the circuit implementation are discussed in detail