Impact of poly field plate dimension towards LDMOS performance

Author

Tee, Elizabeth Kho Ching ; Julai, Norhuzaimin ; Hai, Hu Yong ; Pal, Deb Kumar ; Hua, Tia Swee

Author_Institution

X-FAB Sarawak Sdn. Bhd, Kuching

fYear

2008

fDate

25-27 Nov. 2008

Firstpage

436

Lastpage

440

Abstract

Rapid increasing demand towards high voltage MOSFETs device integrated in low voltage CMOS analog and digital circuits for automobile and power management application has driven the development of 0.18 um high voltage lateral diffused MOSFET (LDMOS) which capable to have 80 V breakdown voltage. During designing this high voltage LDMOS, it is observed that the device performance is very dependent towards the device geometry particularly poly overlap length on STI. Thus, in this paper, the effects of poly overlap length on STI plate for high voltage LDNMOS have been studied extensively during the off-state condition.

Keywords

MOSFET; impact ionisation; semiconductor device breakdown; LDNMOS transistor; breakdown voltage; high voltage MOSFETs; impact ionization; off-state condition; poly field plate dimension; poly overlap length; Analytical models; Automobiles; Breakdown voltage; Circuits; Electric resistance; Immune system; Low voltage; MOSFETs; Medical simulation; Surface resistance; LDMOS; Poly field plate; RESURF; simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on

Conference_Location

Johor Bahru

Print_ISBN

978-1-4244-3873-0

Electronic_ISBN

978-1-4244-2561-7

Type

conf

DOI

10.1109/SMELEC.2008.4770358

Filename

4770358