A compact low power mixed-signal equalizer for gigabit Ethernet applications

Author

Mehrmanesh, Saeid ; Eghbalkha, Behzad ; Saeedi, Saeed ; Afzali-Kusha, Ali ; Atarodi, M.

Author_Institution

Microelectron. Res. & Dev. Centre of Iran

fYear

2006

fDate

21-24 May 2006

Lastpage

5170

Abstract

In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter´s coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 mum CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply

Keywords

CMOS integrated circuits; FIR filters; digital-analogue conversion; discrete time systems; equalisers; local area networks; low-power electronics; mixed analogue-digital integrated circuits; 0.18 micron; 1.8 V; 10 mW; 125 MHz; CMOS technology; FIR filter; analog front end; coefficient rotating structure; digital to analog conversion; discrete time; filter coefficients; gigabit Ethernet applications; high speed dissipation; low power dissipation; low power mixed-signal equalizer; CMOS technology; Circuits; Digital filters; Digital-analog conversion; Equalizers; Ethernet networks; Finite impulse response filter; Merging; Power dissipation; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693796

Filename

1693796