• DocumentCode
    2555260
  • Title

    A novel structure for optimization of switching speed in nanoscale Double Gate Tunnel FET

  • Author

    Mahdi, Vadizadeh ; Morteza, Fathipour

  • Author_Institution
    ECE Dept., Univ. of Tehran, Tehran
  • fYear
    2008
  • fDate
    25-27 Nov. 2008
  • Firstpage
    501
  • Lastpage
    504
  • Abstract
    In this paper, we propose a novel structure for optimizing on/off current ratio in the nanoscale double gate tunneling field effect transistor (DG-TFET). Proposed structure employs an "asymmetric" gate oxide thickness and gate work function engineering which reduces IOFF by 5 orders magnitude without affecting driving current. We discuss the effect of scaling on the ION/IOFF ratio in the proposed structure.
  • Keywords
    CMOS integrated circuits; field effect transistors; CMOS technology; asymmetric gate oxide thickness; complementary metal oxide semiconductor; gate work function engineering; nanoscale double gate tunnel FET; switching speed; Double-gate FETs;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
  • Conference_Location
    Johor Bahru
  • Print_ISBN
    978-1-4244-3873-0
  • Electronic_ISBN
    978-1-4244-2561-7
  • Type

    conf

  • DOI
    10.1109/SMELEC.2008.4770374
  • Filename
    4770374
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2555260