Analytic approach to nullor transformations for FET circuit synthesis. Part I. Nullator-norator tree transformations

A technique for synthesis of all-transistor circuits is to use nullors to represent transistors and then use nullor transformations to ´grow´ the transistor circuit. This approach has the severe problem that the nullor is intrinsically ideal and hence takes no account of non-ideal effects. In this paper and its companion paper, we use the concepts of limit variables and port equivalence in order to treat nullor transformations in an analytic way which encompasses non-ideal effects, categorise them in terms of their effect and identify those that are most suitable for developing circuit designs. Nullator-norator tree transformations are considered here and nullator-norator repairing and cloning transformations in a companion paper