Application of class-F techniques to the design of efficient frequency multipliers

In this paper, class-F technique is suggested for the design of highly efficient frequency multipliers. In addition, the condition of the minimal power consumption at the drain of a transistor is analyzed for class-F frequency tripler case, and its design technique is introduced. In order to minimize the overlapping period of the drain voltage and current waveforms for higher efficiency, the output harmonic network of the frequency tripler is synthesized, and its maximum efficiency was numerically estimated. Finally, a frequency tripler was designed for the input frequency of 840 MHz and the output of 2.475 GHz, of which the output harmonic impedance was optimized for the minimal overlap of the voltage and current waveforms. As a result, the accurate biasing of a transistor and the proper harmonic suppression networks generated the output conversion gain reached to 9.5 dB with the efficiency of 22.9%, which is a well balanced result between the gain and the efficiency as a frequency tripler.