Power efficient rapid hardware development using CoDel and automated clock gating

We present a platform for rapidly developing power efficient hardware architectures. We have developed a new language, called CoDeL, which allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. To estimate the power savings, we have developed an estimation framework, which is shown to be consistent with the power savings obtained using statistical power analysis using Synopsys tools. To evaluate our platform we use the CoDeL implementation of a two-dimensional discrete wavelet transform using the lifting technique. A simulation based power analysis on the designed circuit shows that CoDeL´s clock gating reduces the power dissipation by up to 80%