Title :
Self-aligned double-gate (DG) vertical MOSFET’s using oblique rotating implantation (ORI) method with reduced parasitic capacitance
Author :
Saad, Ismail ; Riyadi, Munawar A. ; Ismail, Riyad ; Arora, Vijay K.
Abstract :
Enhanced symmetrical self-aligned double-gate (DG) vertical nMOSFET with low parasitic capacitance is presented. The process utilizes the oblique rotating ion implantation (ORI) method combined with fillet local oxidation (FILOX) technology (FILOX + ORI). Self-aligned region forms a sharp vertical channel profile that increased the number of electrons in the channel. These have improved drive-on current and drain-induced-barrier-lowering (DIBL) effect with a reduced off-state leakage current tremendously. The gate-to-drain capacitance is significantly reduced while has a small difference of gate-to-source capacitance compared to FILOX device. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs.
Keywords :
MOSFET; capacitance; ion implantation; leakage currents; oxidation; drain overlap capacitance; drain-induced-barrier-lowering effect; fillet local oxidation; gate-drain capacitance; gate-source capacitance; leakage current; oblique rotating ion implantation; reduced parasitic capacitance; self-aligned double-gate vertical MOSFET; source overlap capacitance; CMOS technology; Electrodes; Electronic mail; Epitaxial growth; Insulation life; Ion implantation; MOSFETs; Oxidation; Parasitic capacitance; Silicon;
Conference_Titel :
Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
Conference_Location :
Johor Bahru
Print_ISBN :
978-1-4244-3873-0
Electronic_ISBN :
978-1-4244-2561-7
DOI :
10.1109/SMELEC.2008.4770398
