Characterization analysis of a novel approach in fabrication of CMOS compatible vertical MOSFETs incorporating a dielectric pocket

The process of making novel CMOS compatible vertical MOSFET by incorporating Dielectric Pocket (DP) is shown using virtual wafer simulation tool. The corresponding device doping profiles of a junction is highlighted and demonstrated good device profiles for the feasibility of the approach. The effect of amorph Si recrystallization as the result of different RTA time is also evaluated. Both the transfer and output characteristics of the DP vertical MOSFETs indicates a reasonable value of drive and off -leakage current (ION and IOFF), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The increasing time of RTA to 100 s shows better performance of the device than for shorter time, but in the thread-off of higher drain junction depth and leakage current.