A flexible transform processor architecture for multi-CODECs (JPEG, MPEG-2, 4 and H.264)

Author

Park, Ji Hwan ; Lee, Suh Ho ; Lim, Kyu Sam ; Kim, Jeong Hun ; Kim, Suki

Author_Institution

Dept. of Electr. & Comput. Eng., Korea Univ., Seoul

fYear

2006

fDate

21-24 May 2006

Lastpage

5350

Abstract

This paper proposes a flexible architecture of the transform processor for multi-CODECs (JPEG, MPEG-2, 4 and H.264). Also the memory control scheme to efficiently store intermediate data is presented. In the proposed architecture, four arrays block process at the same time with 4 parallel process elements and pipelined structure for improving the processing time. For verification, FPGA platform with ARM-9 core is used. The results show that the proposed architecture satisfies the requirements of each CODECS such as JPEG, MPEG-2, 4 and H.264 standard

Keywords

distributed memory systems; field programmable gate arrays; flexible electronics; video codecs; video coding; ARM-9 core; FPGA; H.264 standard; JPEG; MPEG-2; MPEG-4; arrays block process; flexible architecture; intermediate data storage; memory control scheme; multiCODEC; pipelined structure; transform processor; Arithmetic; Codecs; Computer architecture; Design methodology; Digital multimedia broadcasting; Discrete cosine transforms; Discrete transforms; Electronic mail; Field programmable gate arrays; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693841

Filename

1693841