A 19.5mW 1.5V 10-bit pipeline ADC for DVB-H systems in 0.35 /spl mu/m CMOS

Author

Adeniran, Olujide A. ; Demosthenous, Andreas

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. Coll. London

fYear

2006

fDate

21-24 May 2006

Abstract

This paper describes a 10-bit analog-to-digital converter (ADC) for digital video broadcasting-handheld (DVB-H) systems. The ADC is based on a 2.5-2.5-2.5-4 bits-per-stage pipeline architecture and occupies an area of 1.3 mm² in a 0.35 mum CMOS process. At the target sampling rate of 20.48 MS/s, measured results show that the converter consumes 19.5 mW from a 1.5 V power supply and achieves 56 dB SNR and 60 dB SFDR. Effective resolution bandwidth is 100 MHz and energy consumption per conversion is 0.19 pJ

Keywords

CMOS integrated circuits; analogue-digital conversion; digital video broadcasting; pipeline processing; 0.35 micron; 1.5 V; 10 bit; 100 MHz; 19.5 mW; CMOS process; DVB-H systems; analog-to-digital converter; digital video broadcasting-handheld systems; energy consumption; pipeline ADC; pipeline architecture; resolution bandwidth; Analog-digital conversion; Bandwidth; CMOS process; Digital video broadcasting; Energy consumption; Energy resolution; Pipelines; Power measurement; Power supplies; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693842

Filename

1693842