Optimized floating point arithmetic unit

Author

Singh, P. ; Bhole, K.

Author_Institution

Instrum. & Control Dept., Coll. of Eng. Pune, Pune, India

fYear

2014

fDate

11-13 Dec. 2014

Firstpage

1

Lastpage

4

Abstract

Arithmetic circuits plays an important role in digital systems. Realization of complex digital circuits is possible with development in very large scale integration (VLSI) circuit technology. In this paper an arithmetic unit based on IEEE-754 standard for floating point numbers has been implemented on Spartan3E XC3S500e FPGA Board. Here Floating Point Unit (FPU) follows IEEE single precision format. Various arithmetic operations such as, addition, subtraction multiplication and division on floating point numbers have been performed on arithmetic unit. Novel approach of converting fixed to floating point saves around 30% of slices and can perform 50 Mega floating point operations per second on Spartan 3E FPGA at 50 MHz clock. Arithmetic operations using proposed conversion optimize space and speed requirements.

Keywords

IEEE standards; VLSI; field programmable gate arrays; floating point arithmetic; IEEE single precision format; IEEE-754 standard; Spartan3E XC3S500e FPGA board; VLSI circuit technology; arithmetic circuits; arithmetic operations; complex digital circuits; digital systems; floating point numbers; optimized floating point arithmetic unit; space requirements; speed requirements; very large scale integration circuit technology; Clocks; Conferences; Field programmable gate arrays; IP networks; Logic gates; Standards; Very large scale integration; FPGA; IEEE 754; floating point numbers; verilog;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference (INDICON), 2014 Annual IEEE

Conference_Location

Pune

Print_ISBN

978-1-4799-5362-2

Type

conf

DOI

10.1109/INDICON.2014.7030552

Filename

7030552