DocumentCode
2556105
Title
Clock jitter compensation for current steering DACs
Author
Wiesbauer, Andreas ; Sträussnigg, Dietmar ; Gaggl, Richard ; Clara, Martin ; Hernandez, Luis ; Gruber, Daniel
Author_Institution
Infineon Technol., Villach
fYear
2006
fDate
21-24 May 2006
Abstract
Clock jitter is an important source of error in highspeed current-steering D/A converters. A technique to compensate these errors is introduced. Simulations show a significant reduction to clock jitter sensitivity for the example of a sigma delta DAC with an analog bandwidth (ABW) of 30 MHz clocked at 360 MHz
Keywords
clocks; digital-analogue conversion; error compensation; jitter; 30 MHz; 360 MHz; analog bandwidth; clock jitter compensation; current steering DAC; errors compensation; sigma delta DAC; Bandwidth; Circuits; Clocks; Delta-sigma modulation; Error correction; Gain measurement; Hardware; Noise measurement; Telematics; Timing jitter;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693848
Filename
1693848
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