Title :
Wafer level monitoring and process optimization for robust via EM reliability
Author :
Zhao, T. ; Shih, C. ; McCollum, J. ; Hawley, Frank ; Issaq, F. ; Cronquist, B. ; Lambertson, R. ; Hamdy, E. ; Yang, Z. ; Chern, C. ; Liao, M. ; Say, G. ; Koh, G. ; Chan, L. ; Sundaresan, R.
Author_Institution :
Actel Corp., Sunnyvale, CA, USA
Abstract :
Via electromigration (EM) lifetime correlates with the initial via resistance. We have found that the single Kelvin via structure is more effective as a wafer-level reliability (WLR) monitor than the via chains. Using this monitor, we have optimized the via process for 0.35 u/0.25 u applications
Keywords :
electromigration; integrated circuit reliability; metallisation; 0.25 micron; 0.35 micron; Kelvin structure; electromigration lifetime; process optimization; reliability; resistance; via; wafer-level monitoring; Electromigration; Foundries; Manufacturing industries; Monitoring; Pulp manufacturing; Robustness; Semiconductor device manufacture; Sputter etching; Temperature distribution; Testing;
Conference_Titel :
Integrated Reliability Workshop Final Report, 1998. IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-4881-8
DOI :
10.1109/IRWS.1998.745360
