The life time model using the correlation between dielectric thickness, and voltage stress for 64 Mb DRAM accelerated reliability testing

Author

Kwon, Yumi ; Cha, Namhyun ; Hwang, Samjin ; Cho, Namsung ; Lee, Whajoon

Author_Institution

Semicond. Bus., Samsung Electron. Co. Ltd., Kyungki, South Korea

fYear

1998

fDate

12-15 Oct 1998

Firstpage

45

Lastpage

48

Abstract

It suggests the life time model of DRAM device which is related with oxide thickness (Tox) and stress voltage. The life time model is composed of the exponential relationship from Mil-HDBK-217E (1986) and the relationship between β (Experimental constant) and Tox which is based on E-Model. This suggested model imply that the life time of packaged device at an ART could be affected by the failure time distribution as well as induced E-field at a given temperature

Keywords

DRAM chips; failure analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; life testing; 64 Mbit; DRAM device; E-Model; accelerated reliability testing; electric field; experimental constant; exponential relationship; failure time distribution; lifetime model; oxide dielectric thickness; voltage stress; Dielectric devices; Electronic equipment testing; Failure analysis; Life estimation; Life testing; Random access memory; Stress; Subspace constraints; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 1998. IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-4881-8

Type

conf

DOI

10.1109/IRWS.1998.745366

Filename

745366