Design and VLSI implementation of a robot navigation processor deploying CORDIC based anti-collision algorithm with RFID technology

Design of a multiplier-less Robot navigation processor with anti-collision and Coordinate Rotation Digital Computer (CORDIC) based algorithm has been presented. The processor, deploying low power wireless Radio Frequency Identification Detection (RFID) technology has been implemented as an efficient VLSI architecture. The hardware of the processor has been realized up to RTL schematic level and fits into a single chip. Xilinx ISE 14.3 design simulation tool and KINTEX-7 FPGA kit have been used for implementation purpose. The performance of the proposed processor has been compared with the existing processor and it reveals improvement in terms of speed, hardware requirement and delay.