Title :
Interconnect reliability test chip NIST 36: for development of measurement tools and standards
Author :
Okuno, Hirotsugu ; Tominaka, T. ; Fujishima, S. ; Mitsumoto, T. ; Kubo, T. ; Kawaguchi, Tatsuki ; Kim, Jung-Wook ; Ikegami, Kenshin ; Sakamoto, Naohisa ; Yokouchi, S. ; Morikawa, T. ; Tanaka, T. ; Goto, Akira ; Yano, Yuichiro
Author_Institution :
Semicond. Electron. Div., Nat. Inst. of Stand. & Technol., Gaithersburg, MD
Abstract :
NIST 36 is a collection of interconnect reliability test structures designed by NIST in collaboration with members of JEDEC Committee JC14.2 on Wafer Level Reliability and with industry researchers. It is a vehicle for improving existing reliability standards and for developing new ones for interconnects that are based on the results of interlaboratory and other experiments. NIST 36 contains a variety of single-level metal and via-type electromigration test structures for evaluating the designs of test structures and their use in test methods to characterize the reliability of interconnects. It also includes structures to measure stress voiding, electromigration-driven noise, metal sheet resistance and linewidth, and oxide thermal conductivity
Keywords :
electromigration; integrated circuit interconnections; integrated circuit measurement; integrated circuit reliability; integrated circuit testing; measurement standards; NIST 36; electromigration test structures; electromigration-driven noise; interconnect reliability test chip; measurement tools; metal sheet resistance; oxide thermal conductivity; standards; stress voiding; Collaboration; Conductivity measurement; Electromigration; NIST; Standards development; Testing; Thermal conductivity; Thermal resistance; Thermal stresses; Vehicles;
Conference_Titel :
Integrated Reliability Workshop Final Report, 1998. IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-4881-8
DOI :
10.1109/IRWS.1998.745382
