Title :
Implementation of H.264/AVC decoder for mobile video applications
Author :
Lee, Suh Ho ; Kim, Jeong Hun ; Park, Ji Hwan ; Kim, Seon Wook ; Kim, Suki
Author_Institution :
Departments of Electron. & Comput. Eng., Korea Univ., Seoul
Abstract :
This paper presents an H.264/AVC baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 30 frames/sec with CIF_(352times288). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (digital multimedia broadcasting) phone
Keywords :
field programmable gate arrays; pipeline processing; reduced instruction set computing; system-on-chip; video coding; 32 bit; AVC decoder; FPGA; H.264 decoder; RISC CPU core; hardware accelerator; mobile video; pipeline processing; system-on-chip; Application software; Automatic voltage control; Decoding; Design methodology; Digital multimedia broadcasting; Hardware; Pipeline processing; Prototypes; Software prototyping; Throughput;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693901
