FPGA and SoC based VLSI architecture of reversible watermarking using rhombus interpolation by difference expansion

This paper presents a VLSI architecture of rhombus interpolation based reversible watermarking by difference expansion. The proposed architecture have been implemented and tested on Xilinx Virtex-7 FPGA, Zynq SoC (System On Chip) and ultra-scale FPGA platforms. The system is based on the modified rhombus interpolation scheme to embed and extract the copyright protection for medical and military imaging applications. In the reversible watermarking, the embedded watermark can be completely extracted along with the original image in a lossless manner. The experimental result of the proposed architectures of the encoding and decoding process for reversible watermarking is implemented using VIVADO 2014.2. The results for quality factors of the original and watermarked image is obtained using MATLAB R2013a and compared with the result generated from hardware implementation in FPGA, SoC and Ultra-scale platform. The results show the viability of low cost, high speed and real-time use of the proposed VLSI architecture.