A 0.18/spl mu/m CMOS 10Gb/s 1:4 DEMUX using replica-bias circuits for optical receiver

Author

Hong, Ju-Pyo ; Ha, Kyung-Soo ; Kim, Lee-Sup

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon

fYear

2006

fDate

21-24 May 2006

Abstract

This paper presents a 0.18mum CMOS 10Gb/s 1:4 demultiplexer using window blocking for stable level swing and replica bias circuit for specific swing level maintenance. A modified current mode logic (CML) is proposed for the high-speed operation of demultiplexer. It prevents holding incorrect data during data transition. Replica bias circuit consists of feedback circuit using simple comparator. The 1:4 demultiplexer is a binary tree type. It consumes 12.24mW in 10Gb/s data rates with 1.8V supply voltage

Keywords

CMOS logic circuits; circuit feedback; comparators (circuits); current-mode logic; demultiplexing equipment; optical receivers; 0.18 micron; 1.8 V; 10 Gbit/s; 12.24 mW; CMOS demultiplexer; binary tree type demultiplexer; comparator; current mode logic; feedback circuit; optical receiver; replica-bias circuits; stable level swing; swing level maintenance; window blocking; CMOS logic circuits; CMOS technology; Capacitance; Circuit simulation; Energy consumption; Feedback circuits; Frequency conversion; Latches; Optical receivers; Pulse inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693931

Filename

1693931