DocumentCode
2558370
Title
Transmission electron microscopy of high threshold voltage, high contact resistance, and high sheet resistance of MOS device
Author
Sheng, Tan Tsu ; Tung, Chih Hang ; Wang, John L F
Author_Institution
Inst. of Microelectron., Singapore
fYear
1997
fDate
21-25 Jul 1997
Firstpage
284
Lastpage
289
Abstract
Transmission electron microscopic examination (TEM) on VLSI process device is presented. Local step coverage and non-uniformity on silicidation has induced high sheet resistance and high contact resistance problems. Native oxide within submicron contacts also increases contact resistivity
Keywords
MOS integrated circuits; VLSI; contact resistance; integrated circuit metallisation; integrated circuit testing; transmission electron microscopy; MOS device; TEM; VLSI process device; contact resistance; local step coverage; native oxide; sheet resistance; silicidation nonuniformity; submicron contacts; threshold voltage; transmission electron microscopy; Conductivity; Contact resistance; Integrated circuit interconnections; MOS devices; Microelectronics; Milling; Silicides; Silicon; Threshold voltage; Transmission electron microscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on
Print_ISBN
0-7803-3985-1
Type
conf
DOI
10.1109/IPFA.1997.638356
Filename
638356
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