Future of CMOS technology

Author

Iwai, Hiroshi

Author_Institution

Frontier Collaborative Res. Center, Tokyo Inst. of Technol., Yokohama, Japan

fYear

2004

fDate

9-10 Sept. 2004

Firstpage

5

Lastpage

17

Abstract

Previously, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In This work, limitation and its possible causes for the downscaling of CMOS are discussed from many aspects.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit manufacture; integrated circuit technology; semiconductor device manufacture; semiconductor technology; 45 nm; 5 nm; CMOS LSI; CMOS downsizing; CMOS technology; complementary metal-oxide-semiconductor; large scale integrated circuits; metal-oxide-semiconductor field effect transistor; p-channel MOSFET; transistor operation; Acceleration; CMOS integrated circuits; CMOS technology; Collaboration; Electronic circuits; Humans; Integrated circuit technology; Large scale integration; MOSFET circuits; Production;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Technology Workshop Proceedings, 2004

Print_ISBN

0-7803-8469-5

Type

conf

DOI

10.1109/SMTW.2004.1393699

Filename

1393699