Modeling and Analyzing the Effect of Microarchitecture Design Parameters on Microprocessor Soft Error Vulnerability

High performance and reliability are essential for microprocessor design. As semiconductor processing technology continues to move toward smaller and denser transistors, lower threshold voltages and tighter noise margins, microprocessors are becoming more susceptible to transient faults (soft errors) that can affect reliability. The increasing chip soft error rates make it is necessary to estimate process transient fault susceptibility at the microarchitecture design stage. Therefore, it becomes important to understand and to evaluate the implications of design choices and optimizations from both performance and reliability perspectives. This paper explores using predictive models to analyze and forecast the effect of various processor microarchitecture design parameters on reliability and their tradeoffs with performance. The most significant factors affecting microarchitecture structures and processor reliability and its runtime variation are obtained. Experimental results show that the proposed modeling techniques can accurately estimate processor reliability, runtime variation, and the performance/reliability tradeoffs in the early stages of microarchitecture design exploration.