Title :
A 40nm 16-core 128-thread SPARC® SoC processor
Author :
Shin, Jinuk Luke ; Huang, Dawei ; Petrick, Bruce ; Hwang, Changku ; Leon, Ana Sonia ; Strong, Allan
Author_Institution :
Oracle, Santa Clara, CA, USA
Abstract :
This fourth generation UltraSPARC T3 SoC processor (code named Rainbow Falls) implements sixteen 8-threaded SPARC cores to double on-chip thread count and throughput performance over its previous generation. It enhances glueless scalability to enable up to 512 threads in a 4-way system configuration. The 16-Bank 6MB L2 Cache, the 512GB/s hierarchical crossbar and the 312-lane SerDes I/O of 2.4Tb/s, support the required high bandwidth. This SoC processor integrates a memory controller, PCIE 2.0, 10Gb Ethernet ports, and support for coherency. Multiple clock and power domains optimize performance and power for the SoC components. Extensive power management features, from architecture to circuit techniques, minimize both active and idle power. The 377mm2 die includes 1 billion transistors in a flipchip ceramic package with 2117 pins. The chip is fabricated in TSMC´s 40nm high performance process with 11 Cu metals and four transistor types.
Keywords :
cache storage; ceramic packaging; copper; flip-chip devices; microprocessor chips; system-on-chip; transistors; 16-bank L2 cache; 16-core 128-thread SPARC SoC processor; 4-way system configuration; Cu; Ethernet ports; PCIE 2.0; Rainbow Falls; SerDes I-O; TSMC high-performance process; bit rate 512 Gbit/s; circuit techniques; clock domains; copper metals; flipchip ceramic package; fourth generation UltraSPARC T3 SoC processor; glueless scalability; hierarchical crossbar; memory controller; on-chip thread count; power domains; power management; size 40 nm; transistors; Clocks; Phase locked loops; Synchronization; System-on-a-chip; Throughput; Transistors; Yarn;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716541