Source-drain engineering for Sub-90 nm junction-field-effect transistors

This paper presents sub-90 nm symmetric and asymmetric source-drain junction-field-effect transistor (JFET) devices for ultra-low voltage operation. The JFET devices are suitable for ultra-low voltage analog applications by overcoming the limitations of advanced MOSFET devices and CMOS technologies. However, the performance of sub-90 nm channel-JFETs is limited by higher off-state leakage current and lower ON/OFF current ratio. In this paper, we introduce asymmetric source-drain device architecture to improve the ON/OFF performance of JFET devices. The numerical device simulation results show that the proposed asymmetric devices significantly reduce the off-state leakage current in contrast to the symmetric devices for high performance operation at ultra-low power supply voltage of 0.5 V.