Title :
A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction
Author :
Zhang, Xin ; Pu, Yu ; Ishida, Koichi ; Ryu, Yoshikatsu ; Okuma, Yasuyuki ; Chen, Po-Hung ; Watanabe, Kazunori ; Sakurai, Takayasu ; Takamiya, Makoto
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
Abstract :
To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a novel feedback control scheme is presented. The proposed scheme uses pulse density and width modulation (PDWM) to reduce the output ripple with low output voltage. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional pulse density modulation (PDM), the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.
Keywords :
CMOS integrated circuits; DC-DC power convertors; PWM power convertors; feedback; switched capacitor networks; CMOS process; current 0.25 mA to 10 mA; efficiency penalty; feedback control; pulse density modulation; pulse width modulation; ripple reduction; size 65 nm; switched-capacitor DC-DC converter; voltage 0.2 V to 0.47 V; voltage 1 V; Capacitors; Clocks; Converters; Current measurement; Switches; Switching circuits; Voltage measurement;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716557
