Title :
Thin relaxed SiGe layers for strained Si CMOS
Author :
Chen, P.S. ; Lee, S.W. ; Lee, M.H. ; Liu, C.W. ; Tsai, M.J.
Author_Institution :
Electron. Res. & Service Organ., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
High quality, low cost and smooth surface of thin relaxed SiGe layers on new buffers are fabricated. This SiGe nanostructure buffers help thin SiGe uniform layers to relax by introducing some dislocations networks. With these novel Si/Ge buffer, the reduction of thickness of relaxed SiGe uniform layer are from 50 to 75%. The mobility enhancement of the strained Si n-MOSFET deposited on theses relaxed SiGe layer/SiGe buffers are 8 to 40% higher than that of controlled compositional graded SiGe buffers. Such thin relaxed SiGe layers on these new buffers prove to be useful approach to fabricate high quality relaxed epilayers with large lattice mismatch.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; buffer layers; integrated circuit manufacture; nanostructured materials; semiconductor materials; CMOS; SiGe; complementary metal-oxide-semiconductor; lattice mismatch; metal-oxide-semiconductor field effect transistor; mobility enhancement; n-MOSFET; nanostructure buffers; Atomic force microscopy; CMOS technology; Capacitive sensors; Costs; Germanium silicon alloys; MOSFET circuits; Rough surfaces; Silicon germanium; Surface roughness; Transistors;
Conference_Titel :
Semiconductor Manufacturing Technology Workshop Proceedings, 2004
Print_ISBN :
0-7803-8469-5
DOI :
10.1109/SMTW.2004.1393727
