A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation

Author

Deng, Wei ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2010

fDate

8-10 Nov. 2010

Firstpage

1

Lastpage

4

Abstract

This paper investigates the adoption of LC-VCO to replace ring VCO for ultra-low-voltage sub-picosecond jitter clock generation in future 0.5-V LSI and power aware LSI. A 0.5-V LC-VCO using E-TSPC frequency divider with forward body bias technique is proposed and implemented. Significant performances, in terms of 0.6-ps jitter, 50 MHz-to-6.4 GHz frequency tuning range with 2 bands and sub-1mW P_DC, have been achieved in the measurement results.

Keywords

MMIC oscillators; UHF oscillators; frequency dividers; jitter; large scale integration; voltage-controlled oscillators; E-TSPC frequency divider; LC-VCO; UHF oscillators; forward body bias; frequency 0.05 GHz to 3.2 GHz; frequency 4.1 GHz to 6.4 GHz; microwave oscillators; power aware LSI; sub-picosecond-jitter clock generation; voltage 0.5 V; voltage-controlled oscillators; CMOS integrated circuits; Clocks; Frequency conversion; Jitter; Power supplies; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian

Conference_Location

Beijing

Print_ISBN

978-1-4244-8300-6

Type

conf

DOI

10.1109/ASSCC.2010.5716565

Filename

5716565