Title :
Deep Sub-100 nm Design Challenges
Author_Institution :
Toshiba Corp., Kawasaki
Abstract :
This paper will describe the problems in the design and development of deep sub-100 nm system LSI´s and/or SoC´s. One of the most difficult problems is the large power consumption, in both active and stand-by modes. Another problem is how to improve the development efficiency of large scale chips and related softwares. Lithography, that has been getting harder and harder, directly impacts the chip yield. Several approaches to these problems will be discussed; various low power technologies from circuit to architecture levels, high-level language based design flow, IP reuse platform and DFM (Design for Manufacturing) related technologies.
Keywords :
circuit CAD; design for manufacture; integrated circuit design; large scale integration; lithography; logic CAD; system-on-chip; IP reuse platform; LSI; SoC; deep sub-100 nm system; design for manufacturing; high-level language based design flow; large scale chips; lithography; size 100 nm; Driver circuits; Energy consumption; Large scale integration; Large-scale systems; Leakage current; MOSFETs; Moore´s Law; Random access memory; Research and development; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location :
Hangzhou
Print_ISBN :
0-7803-9734-7
Electronic_ISBN :
0-7803-97375-5
DOI :
10.1109/ASSCC.2006.357838
