Title :
Alleviating routing congestion by combining logic resynthesis and linear placement
Author :
Liu, Shihming ; Pan, Kuo-Rueih ; Pedram, Massoud ; Despain, Alvin M.
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
In this approach, the logic is restructured using an intermediate placement solution and then the placement is adjusted to match the new logic structure. This ability to change logic structure during layout allows one to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been resynthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared to the original designs
Keywords :
circuit layout CAD; circuit optimisation; logic CAD; logic gates; minimisation of switching nets; multivalued logic circuits; network routing; LRAP; algorithmic restructuring technique; bit-sliced layout; channel density reductions; intermediate placement solution; layout area optimiser; linear placement; logic resynthesis; multilevel logic; prototype program; routing congestion; routing optimisation; Circuit synthesis; Contracts; Equations; Integrated circuit interconnections; Logic circuits; Logic design; Prototypes; Routing; Timing; Very large scale integration;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386413