DocumentCode
2559658
Title
A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC
Author
Miyahara, Masaya ; Lin, James ; Yoshihara, Kei ; Matsuzawa, Akira
Author_Institution
Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
fYear
2010
fDate
8-10 Nov. 2010
Firstpage
1
Lastpage
4
Abstract
An ultra-low voltage operation of 0.5 V, 5-bit Flash ADC has been developed and achieved an ENOB of 4.2-bit at a conversion rate of 600 MS/s. It consumes only 1.2 mW and attained an ultra-low FoM of 160 fJ/conv. steps at an ERBW of 200 MHz. A forward body bias technique and gate-interpolated double-tail latched comparator with variable delay method to compensate the mismatch voltage are introduced.
Keywords
analogue-digital conversion; comparators (circuits); ENOB; ERBW; FoM; figure-of-merit; flash analog-digital converters; forward body bias technique; gate-interpolated double-tail latched comparator; mismatch voltage; power 1.2 mW; variable delay method; voltage 0.5 V; word length 5 bit; CMOS integrated circuits; Capacitance; Delay; Frequency conversion; Layout; Logic gates; Power demand;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location
Beijing
Print_ISBN
978-1-4244-8300-6
Type
conf
DOI
10.1109/ASSCC.2010.5716584
Filename
5716584
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