• DocumentCode
    2559659
  • Title

    A sea-of-gates-based, 10 MIPS 16-bit RISC processor testbed for failsafe applications

  • Author

    Jurczyk, Michael ; Schwederski, Thomas

  • Author_Institution
    Inst. for Microelectron. Stuttgart, Germany
  • fYear
    1993
  • fDate
    22-25 Feb 1993
  • Firstpage
    536
  • Lastpage
    540
  • Abstract
    A sea-of-gates-based, 16-bit RISC processor testbed with a maximum performance of 10 MIPS at a 20 MHz clock rate is described. Starting from a small core requiring only 3000 gates, features can be added in a flexible manner to obtain various system architectures suited for failsafe applications. The core has a load-store Harvard architecture with 24-bit instructions, a 16-bit data path, and a two-stage pipeline. The data path contains sixteen 16-bit general purpose registers and a high-speed 16-bit carry-select adder. The core version has been fabricated on a 1.2 mm GATE FOREST master. An experimental version with control flow checking, boundary scan capability with integrated pad-test and 100% stuck-fault coverage is in fabrication. Software support includes high-level and RT-level simulators, assembler and PASCAL-compiler
  • Keywords
    application specific integrated circuits; automatic test software; boundary scan testing; built-in self test; computer testing; integrated circuit testing; logic arrays; logic testing; reduced instruction set computing; 10 MIPS; 16 bit; 20 MHz; GATE FOREST master; PASCAL-compiler; RISC processor testbed; RT-level simulators; assembler; boundary scan capability; carry-select adder; control flow checking; failsafe applications; general purpose registers; high-level simulator; integrated pad-test; load-store Harvard architecture; microprocessor core; sea-of-gates-based; semicustom; two-stage pipeline; Automatic testing; Central Processing Unit; Circuit faults; Circuit testing; Hardware; Integrated circuit testing; Microprocessors; Reduced instruction set computing; Switches; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
  • Conference_Location
    Paris
  • Print_ISBN
    0-8186-3410-3
  • Type

    conf

  • DOI
    10.1109/EDAC.1993.386420
  • Filename
    386420