A 1.5MS/s 6-bit ADC with 0.5V supply

Author

Gambini, Simone ; Rabaey, Jan

Author_Institution

Univ. of California at Berkeley, Berkeley

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

47

Lastpage

50

Abstract

A moderate resolution analog-to-digital converter targeting wireless sensor networks applications is presented. Employing a successive approximation architecture, the device achieves 6 bits of resolution at 1.5 MS/s output rate, while drawing 28muA from a low 0.5 V supply, corresponding to a Figure of Merit (FOM) of .25pJ/conversion step. Low-density metal5-metal6 capacitors guarantee feedback DAC linearity while minimizing input capacitance, while the use of a passive sample and hold, combined with a class-AB comparator reduce analog power dissipation to 4muW (30% of the total). The analog core is operational for supply values as low as .3V, even though sampling rate is reduced to 175kS/s.

Keywords

analogue-digital conversion; capacitors; feedback; wireless sensor networks; analog power dissipation; analog-to-digital converter; capacitors; feedback; voltage 0.5 V; wireless sensor networks; CMOS technology; Capacitors; Circuits; Feedback; Power dissipation; Receivers; Sampling methods; Switches; Voltage; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357848

Filename

4197587