A design methodology achieving fast development cycles for complex VLSI architectures

Author

Wollan, Vegard

Author_Institution

Nordic VLSI, Flatasen, Norway

fYear

1993

fDate

22-25 Feb 1993

Firstpage

532

Lastpage

535

Abstract

A design methodology that accomplishes fast design cycles for complex VLSI circuits and maintains a high level of integration and performance is presented. A configurable RISC microprocessor is the system core. Flexible and regular cells are used to automatically generate digital and analog hardware blocks. Together with this pick-and-place design methodology of the system architecture, a high-level development system leads to shortened design times

Keywords

circuit CAD; circuit layout CAD; circuit optimisation; computer architecture; design engineering; high level synthesis; integrated circuit design; microprocessor chips; reduced instruction set computing; ASIC; D2-MAC/PACKET chip set; analog hardware blocks; complex VLSI architectures; configurable RISC microprocessor; configurable on-chip core microprocessor; design methodology; digital hardware blocks; fast development cycles; high level of integration; high performance; high-level development system; macro assembler; optimizing C compiler; pick-and-place design; shortened design times; Application specific integrated circuits; Costs; Design methodology; Hardware; Microprocessors; Prototypes; Read only memory; Registers; Software prototyping; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386421

Filename

386421