A Dual Low Power 1/2 LSB NL 16b/1Msample/s SAR A/D Converter with on-chip Microcontroller

Author

Leung, Ka Y. ; Leung, Kafai ; Holberg, Douglas R.

Author_Institution

Silicon Lab. Inc., Austin

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

51

Lastpage

54

Abstract

A 0.35 mum double-poly CMOS 16 b SAR A/D converter uses self-calibration techniques to obtain frac12 LSB INL. The differential and single-ended THD at 1Msample/s are 101dB and 96 dB, respectively. Each ADC consumes 20 mW at 3 V and occupies 2.9 mm² active area, resulting in a 0.9 pJ/b FOM. The chip includes 3 ADCs, 2 DACs, 8051-microcontroller, CAN controller, DMA controller, 64 K flash memory and 4 K RAM occupying 26 mm².

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; digital-analogue conversion; flash memories; harmonic distortion; microcontrollers; random-access storage; ADC; CAN controller; DAC; DMA controller; LSB INL; RAM; differential THD; double-poly CMOS SAR A/D converter; flash memory; on-chip microcontroller; power 20 mW; self-calibration techniques; single-ended THD; size 0.35 mum; voltage 3 V; word length 16 bit; Calibration; Capacitance; Capacitors; Circuits; Flash memory; Microcontrollers; Process control; Read-write memory; System-on-a-chip; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357849

Filename

4197588