DocumentCode
2559736
Title
A low-cost, leakage-insensitive semi-digital PLL with linear phase detection and FIR-embedded digital frequency acquisition
Author
He, Rui ; Liu, Chengwen ; Yu, Xueyi ; Rhee, Woogeun ; Park, Joon-Young ; Kim, Changhyun ; Wang, ZhiHua
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear
2010
fDate
8-10 Nov. 2010
Firstpage
1
Lastpage
4
Abstract
A semi-digital PLL utilizing a hybrid DCO is presented. A mixed-mode loop control with an analog proportional path and a digital integration path provides linear phase tracking, leakage-insensitive loop filtering, and technology scalability. With the absence of the linear TDC, the semi-digital PLL with the hybrid DCO can relax design difficulties such as achieving low power or requiring an advanced CMOS technology. Also, the hybrid finite-impulse response (FIR) filtering method is employed to reduce the DCO quantization noise without causing latency. The prototype PLL implemented in 0.18 μm has the active area of 0.6 mm2 where only 0.01 mm2 is occupied by the analog loop filter.
Keywords
FIR filters; linear phase filters; mixed analogue-digital integrated circuits; phase locked loops; FIR-embedded digital frequency acquisition; analog proportional path; digital integration path; hybrid DCO; hybrid finite-impulse response filtering method; leakage-insensitive semi-digital PLL; linear phase detection; linear phase tracking; mixed-mode loop control; size 0.18 mum; Finite impulse response filter; Frequency modulation; Noise; Phase locked loops; Quantization;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location
Beijing
Print_ISBN
978-1-4244-8300-6
Type
conf
DOI
10.1109/ASSCC.2010.5716589
Filename
5716589
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